Dynamic Random Access Memories (DRAMs) are commonly used in digital computers to store data. DRAMs have significantly greater storage density than Static Random Access Memories (SRAMs) but operate at slower speeds than SRAMs.
A number of techniques have been developed to improve the access time of memory systems employing DRAM chips. A common technique is the use of page mode addressing which exploits the internal organization of the DRAM. Specifically, typical DRAM chips employ a storage array organized in rows (also known as "pages") and columns. Presentation of a row address causes access of an entire row, which includes a plurality of columns, to a Bit-Line Sense Amplifier (BLSA). Presentation of a column address then causes selection and output from the chip of a column comprising one or more bits. The row access typically is the significant limiting factor in a data access from a DRAM. Once the row access is performed, multiple column accesses may be performed to implement the aforesaid page mode operation.
Page mode operation provides significant increases in the speed of reading from and writing to a DRAM. However, such an increase only occurs so long as all accesses are within a particular row, or page. Whenever an access occurs across a row/page boundary, a performance penalty is incurred. What is needed is a system whereby a performance penalty is not necessarily incurred when an access occurs which crosses a row/page boundary.